Power IC Design Engineer

Location: Sydney, Australia

About Us:

• Silanna’s global design group is working on the development of cutting-edge DC-DC solutions.
• We are looking for a Power IC Design Engineer to join our Sydney based team.
• This represents and exciting opportunity for a talented motivated young engineer to join a collaborative team and gain experience in various analog cell designs for high-efficiency DC-DC and AC-DC power converters. You will work in an environment where you will share and discuss your design ideas and with support from the senior engineering team, work towards their implementation on silicon.

About the Role:

The IC Design Engineer will be responsible for designing analog and mixed signal blocks for integrated POL, Multiphase and PMIC power management products. Mentors will be available to guide and advise as needed, but some level of autonomy is expected with respect to design, investigation, simulation and professional development. There will also be some limited level of interaction with cross-functional teams such as Applications & Test Engineering.

The Power IC Design Engineer will have a variety of responsibilities including:

• Participation in several aspects of the design cycle, including transistor level design, layout supervision, lab debug of your cells
• Research and development of state-of-the-art analog and mixed signal products for selected markets
• Work with other members of Design to develop Power Management Cell IP including but not limited to Buck Regulators, Boost Regulators, LDO, Bandgap, Voltage and Current References, Clock, bias circuitry, etc.
• Development of products to meet the performance and cost targets on time
• Preparation of cell IP support documents. Present cell IP to peers
• Provision of guidelines to Mask designers on circuit layout
• Authoring of characterization and cell test plans for the IPs and Product

About You:

Qualifications and Education Requirements:

• BSEE Required; MSEE preferred.
• Any professional experience in analog and mixed signal IC design of power management circuits is a plus. (1-5 years would be ideal).
• Strong knowledge of analog integrated circuit fundamentals
• Strong knowledge of CMOS device physics and fabrication processes
• Knowledge of parasitic and noise analysis
• Knowledge of best Layout practices
• Self-motivated, driven, and passionate individual with focus on results and meeting project schedules
• VerilogA or AVHDL language and simulation verification experience is a plus
• Mixed-signal simulation, interfacing with analog functions – Fluent with Cadence design environment
• Must possess strong written and verbal communication skills

Only candidates with existing Australian working rights will be considered.