Senior Power IC Design Engineer

Location: Sydney, Australia

About Us:

• Silanna’s global design group is working on the development of cutting-edge DC-DC solutions.
• We are looking for a Senior Power IC Design Engineer to join our Sydney based team. Working on product design from the ground up through all phases, potentially including tapeout.
• This is an exciting opportunity for a motivated person to grow existing experience in precise analog cells and DC-DC converter design.

About the Role:

The Senior Power IC Design Engineer will be responsible for designing analog and mixed signal cells and at times leading the design of integrated POL, Multiphase and PMIC power management products. These products address the needs of consumer handheld, portable, server and telecom markets, and as such this candidate must have experience in the development of products intersecting one or several of these markets.

The Senior Power IC Design Engineer will have a variety of responsibilities including:

• Participate in all aspects of the design cycle, including architecture development, transistor level design, layout supervision, lab debug and product characterization
• Research and development of state-of-the-art analog and mixed signal products for selected markets
• Developing IP including but not limited to Buck Regulators, Boost Regulators, LDOs, Bandgaps, Voltage and Current References, Clocks, Bias circuitry, etc.
• Process Selection, circuit design, system modeling, top level simulation, corner simulation, and design verification
• Provide guidelines to layout designers on circuit and full chip layout
• Author characterization and test plans for the IPs and Product.
• Support Test engineers on products you lead
• Support of new product release and FA

About You:

Qualifications and Education Requirements:

• BSEE Required; MSEE or PhD preferred.
• 5+ years professional experience in analog and mixed signal IC design of power management Voltage Regulator IC products for POL, Multiphase and PMIC architectures serving Server, Telecom, Portable and Handheld Markets.
• Proven experience with high bandwidth error amplifier design and precision bandgap, and current balance/sensing design.
• Solid technical knowledge of power semiconductor IC design including PMIC and POL voltage regulators.
• Self-motivated, driven, and passionate individual with focus on results and meeting project schedules.
• Strong knowledge of CMOS device physics and fabrication processes.
• Strong knowledge of analog integrated circuit fundamentals.
• Strong knowledge of parasitic and noise analysis skills.
• Verilog/VHDL language and simulation verification experience is a plus
• Mixed-signal simulation, interfacing with analog functions – Fluent with Cadence design environment.
• Strong written and verbal communication skills.

Only candidates with existing Australian working rights will be considered.